Wrap Processing - Self Improving Chip Performance

Via physorg.com -

A new, patent-pending technology developed over the last five years by UCR’s Frank Vahid, Professor of Computer Science and Engineering, called "Warp processing" gives a computer chip the ability to improve its performance over time.

The benefits of Warp processing are just being discovered by the computing industry. A range of companies including IBM, Intel and Motorola’s Freescale have already pursued licenses for the technology through UCR’s funding source, the Semiconductor Research Corporation.

Here’s how Warp processing works: When a program first runs on a microprocessor chip (such as a Pentium), the chip monitors the program to detect its most frequently-executed parts. The microprocessor then automatically tries to move those parts to a special kind of chip called a field-programmable gate array, or FPGA. “An FPGA can execute some (but not all) programs much faster than a microprocessor – 10 times, 100 times, even 1,000 times faster,” explains Vahid.

“If the microprocessor finds that the FPGA is faster for the program part, it automatically moves that part to the FPGA, causing the program execution to ‘warp.’” By performing optimizations at runtime, Warp processors also eliminate tool flow restrictions, as well as the extra designer effort associated with traditional compile-time optimizations.

FPGAs can benefit a wide range of applications, including video and audio processing; encryption and decryption; encoding; compression and decompression; bioinformatics – anything that is compute-intensive and operates on large streams of data. Consumers who want to enhance their photos using Photoshop or edit videos on their desktop computers will find that Warp processing speeds up their systems, while gamers will immediately notice the difference in better graphics and performance. Additionally, embedded systems such as medical instrument or airport security scanners can perform real-time recognition using Warp-enhanced FPGAs.

“Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators” was named one of the top five papers at the 2007 International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS) conference in Austria, and was published among the conference proceedings. “Warp Processing and Just-in-Time FPGA Compilation,” the Ph.D. dissertation of Vahid’s student Roman Lysecky, was named “Dissertation of the Year” by the European Design and Automation Association in 2006.

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Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators (PDF)